Module not found error in Verilog

My testbench module reference code is giving this error:

Module "quad_seven_seg" not found while processing module instance "my_quad"

I have instantiated the quad_seven_seg in the test bench with my_quad.

module quad_seven_seg (
  input wire clk,
  input wire [3:0] val0,
  input wire dot0,
  output reg an3,
  output reg an2,
  output reg an1,
  output reg an0,
  output wire ca,
  output wire cb,
  output wire cc,
  output wire cd,
  output wire ce,
  output wire cf,
  output wire cg,
  output wire dp,
  output wire [3:0] vcc
  );

assign vcc = 4'b1111;
assign {ca, cb, cc, cd, ce, cf, cg} = SevenSeg;

reg [3:0] BCD;
reg [7:0] SevenSeg;

always @(*)
 case(BCD)
  4'h0: SevenSeg = 8'b11111100;
  4'h1: SevenSeg = 8'b01100000;
  4'h2: SevenSeg = 8'b11011010;
  4'h3: SevenSeg = 8'b11110010;
  4'h4: SevenSeg = 8'b01100110;
  4'h5: SevenSeg = 8'b10110110;
  4'h6: SevenSeg = 8'b10111110;
  4'h7: SevenSeg = 8'b11100000;
  4'h8: SevenSeg = 8'b11111110;
  4'h9: SevenSeg = 8'b11110110;
  SevenSeg = 8'b00000000;
 endcase                  
endmodule       

The Test bench

  `timescale 1 ns / 1 ps
  module testbench_v;
  wire an3, an2, an1, an0;
  wire ca, cb, cc, cd, ce, cf, cg, dp;
 reg [3:0] /*val3, val2, val1,*/ val0;
 reg dot3, dot2, dot1, dot0;
 reg clk;

Instantiating the quad_seven_seg module with my_quad.

 quad_seven_seg my_quad(
 .clk(clk),
 .val0(val0),
 .dot0(dot0),
 .an3(an3),
 .an2(an2),
 .an1(an1),
 .an0(an0),
 .ca(ca),
 .cb(cb),
 .cc(cc),
 .cd(cd),
 .ce(ce),
 .cf(cf),
 .cg(cg),
 .dp(dp),
 .vcc(vcc)
   );

 always
 begin
  clk = 1'b0;
  #5;
  clk = 1'b1;
  #5;
 end

initial
 begin
  $display("If simulation ends before the testbench");
  $display("completes, use the menu option to run all.");
  val0 <= 4'h0;
  dot0 <= 1'b1;
  $display("Prepare to wait a long time...");
  #5000000;
  $display("Checkpoint, simulation time is %t",$time);
  #5000000;
  $display("Checkpoint, simulation time is %t",$time);
  #5000000;
  $display("Checkpoint, simulation time is %t",$time);
  #5000000;
  $display("Checkpoint, simulation time is %t",$time);
  #5000000;
  $display("Checkpoint, simulation time is %t",$time);
  // End the simulation.
$display("Simulation is over, check the waveforms.");
$stop;
end

endmodule

Where I am going wrong?