Testing VHDL / FPGA Using Python and A Simulator

The standard way to test VHDL code logic is to write a test bench in VHDL and utilize a simulator like ModelSim; which, I have done numerous times.

I have heard that instead of writing test benches in VHDL, engineers are now using Python to test there VHDL code.

Questions:

1. How is this done?

   • Is this done by writing a test bench in Python and then compiling this Python file or linking into Modelsim?
   • Is this done in Python using a module like myHDL and then linking/importing your VHDL file into Python? Is so, how is the timing diagram generated?

2. When writing a test bench in Python can you use standard Python coding/modules or just a module like myHDL?

   • For example if I want to test a TCP/IP stack in VHDL, can I use the socket module in Python to do this (i.e. import socket)?

3. Is there a reference, paper, or tutorial that shows how to do this? I've checked the Xilinx, Altera, and Modelsim websites but could not find anything.

The only thing I find online about using Python for FPGA are a few packages: with myHDL being the most referenced.