How to deal whith VHDL generics in code coverage

When testing a digital architecture written in VHDL and aiming for 100% code coverage, I don't really know how to deal with generic inputs.

In my case, I have a single component with generic-dependant behaviour that is instantiated twice. The instance have different ('0' and '1') values for this generic, which is meant to be and cannot be otherwise. Because of this, my code coverage cannot be 100 % (the generic value will always be '1' for one instance and '0' for the other).

I know I could decide to exclude verifications from the coverage but I'm not sure this is the best way to do. What is considered best practise in this case?