Verilog HDL syntax error near "default", expecting "endmodule"

// ProgramCounterTestBench

`timescale 1ns / 1ps

module ProgramCounterTestBench();

logic               Clock = 0;
logic               Reset = 0;
logic        [15:0] LoadValue;
logic               LoadEnable;
logic signed  [8:0] Offset;
logic                   OffsetEnable;
logic signed  [15:0]    CounterValue;


ProgramCounter uut
(
    .Clock,
    .Reset,
    .LoadValue,
    .LoadEnable,
    .Offset,
    .OffsetEnable,
    .CounterValue
);

default clocking @(posedge Clock);
endclocking

always  #10  Clock = ~Clock;

initial
    begin
        ##1 Reset = 1;
        ##1 Reset = 0;
    end

endmodule

I'm trying to create a test bench for a program counter to test out if it counts and resets, but i keep getting these errors:

Error (10170): Verilog HDL syntax error at ProgramCounterTestBench.sv(15) near text: "default"; expecting "endmodule". Error (10170): Verilog HDL syntax error at ProgramCounterTestBench.sv(37) near text: "##"; expecting "end". Error (10170): Verilog HDL syntax error at ProgramCounterTestBench.sv(38) near text: "##"; expecting "end".

Since i clearly have an endmodule I'm assuming there must be something wrong with my use of default clocking, can someone point out how to correct it?