Create a Verilog Test Fixture file

I've written the program for the Hamming Code, but I used in the second module the informations from the first one. The problem is that I have to create 2 Test files, one for each module. For the first one, hamming_encoder, the program runs perfectly. But I don't know how to write the code in Verilog for the second one, since is needs the output from the first module. Here is the code:

module hamming_encoder(
output [16:1] out,
input [10:0] in
);

assign out[16] = in[0] ^ in[2] ^ in[4] ^ in[6] ^ in[7] ^ in[9] ^ in[10];
assign out[15] = in[0] ^ in[1] ^ in[4] ^ in[5] ^ in[7] ^ in[8] ^ in[10];
assign out[14] = in[10];
assign out[13] = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[7] ^ in[8] ^ in[9];
assign out[12] = in[9];
assign out[11] = in[8];
assign out[10] = in[7];
assign out[9] = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6];
assign out[8] = in[6];
assign out[7] = in[5];
assign out[6] = in[4];
assign out[5] = in[3];
assign out[4] = in[2];
assign out[3] = in[1];
assign out[2] = in[0];
assign out[1] = out[16] ^ out[2] ^ out[3] ^ out[4] ^ out[5] ^ out[6] ^ out[7] ^ out[8] ^ out[9] ^ out[10] ^ out[11] ^ out[12] ^ out[13] ^ out[14] ^ out[15];    

endmodule

module hamming_decoder(
output reg [10:0] out,
output reg [3:0] error_index,
output reg error,
output reg uncorrectable,
input [16:1] in
);

reg y; // in case "single error", gives the position of the error bit    
reg [1:0] check; // if check[0] = 0 - no error
                  // if check[0] = 1 and check[1] = 0 => double error
                  // if check[0] = 1 and check[1] = 1 => single error

reg [16:1] out_encoder; 
reg [10:0] in_encoder;                    

assign error_index[0] = in[16] ^ in[14] ^ in[12] ^ in[10] ^ in[8] ^ in[6] ^ in[4] ^ in[2];
assign error_index[1] = in[15] ^ in[14] ^ in[11] ^ in[10] ^ in[7] ^ in[6] ^ in[3] ^ in[2];
assign error_index[2] = in[13] ^ in[12] ^ in[11] ^ in[10] ^ in[5] ^ in[4] ^ in[3] ^ in[2];
assign error_index[3] = in[9] ^ in[8] ^ in[7] ^ in[6] ^ in[5] ^ in[4] ^ in[3] ^ in[2];

hamming_encoder hamming_encoder_instance(.out(out_encoder), .in(in_encoder));

assign check[1] = out_encoder[1] ^ in[1];   

always @(*)
begin
    if (error_index[0] != 0 || error_index[1] != 0 || error_index[2] != 0 || error_index[3] != 0)
        begin
            check[0] = 1;
            error = 1;
        end

    if (check[0] == 0)
        begin
            error = 0;
            uncorrectable = 0;
            out[0] = in[1];
            out[1] = in[2];
            out[2] = in[3];
            out[3] = in[4];
            out[4] = in[5];
            out[5] = in[6];
            out[6] = in[7];
            out[7] = in[9];
            out[8] = in[10];
            out[9] = in[11];
            out[10] = in[13];
        end
            else if(check[1] == 0)
                    begin
                        error = 1;
                        uncorrectable = 1;
                        out[0] = in[3];
                        out[1] = in[5];
                        out[2] = in[6];
                        out[3] = in[7];
                        out[4] = in[9];
                        out[5] = in[10];
                        out[6] = in[11];
                        out[7] = in[12];
                        out[8] = in[13];
                        out[9] = in[14];
                        out[10] = in[15];
                    end
                else if (check[1] == 1 && check[0] != 0)
                            begin
                                error = 1;
                                uncorrectable = 0;
                                y = error_index[0] + error_index[1] * 2 + error_index[3] * 4 + error_index[4] * 8;
                                out[0] = in[3];
                                out[1] = in[5];
                                out[2] = in[6];
                                out[3] = in[7];
                                out[4] = in[9];
                                out[5] = in[10];
                                out[6] = in[11];
                                out[7] = in[12];
                                out[8] = in[13];
                                out[9] = in[14];
                                out[10] = in[15];
                                out[y-1] = !out[y-1]; // ?
                            end
    end

endmodule