Is it possible to access components of the uut in VHDL Testbench?

I want to write a testbench for a module that instantiates several components but has no significant outputs. To test the correctness I'd have to access variables of components of the uut. At least being able to access variables of the uut would be helpful.

I would imagine that to work a little like this:

uut: top_module port map(
              i_clk => clk,
              i_reset => reset
      );
testbench: process
begin
    wait for CLK_PERIOD;
    report  STD_LOGIC'image(top_module.flag) severity note;
end process;

Of course I can write the testbench in a way that it replaces the top module but then I wouldn't be able to test that model. Expanding the output of the top module/uut is also not really an option.