Verilog === Operator Not Working

I have a wire:

wire module3Output;

In the end, I test the binary on the wire using:

if (module3Output === 1)
    #1 $display("PASS: module3Output=%b", module3Output);
else
    #1 $display("FAIL: module3Output=%b", module3Output);

Output:

FAIL: module3Output=1

Why is it failing when it clearly shows module3Output=1?

I can post full code if required.