Simple test bench in vhdl with generic

I have very simple 'program' written in VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std;


entity Xand is
    generic(width   : integer:=8);
    port(   clk : in std_logic;
        A,B : in std_logic_vector(width-1 downto 0);
        C   : out std_logic_vector(width-1 downto 0)
    );
end Xand;

architecture Behavioral of Xand is
begin
    C<= A and B;
end Behavioral;

and one test bench for it, where i have to use generic:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;

ENTITY Xand_tb IS

END Xand_tb;

ARCHITECTURE behavior OF Xand_tb IS 

    COMPONENT Xand IS
        generic(width   : integer);
        port(   clk : in std_logic;
            A,B : in std_logic_vector(width-1 downto 0);
            C   : out std_logic_vector(width-1 downto 0)
        );
    end COMPONENT;

    signal width : integer := 8;

   -- inputs
   signal clk : std_logic := '0';
   signal A, B : std_logic_vector(width-1 downto 0);

   --Outputs
   signal C : std_logic_vector(width-1 downto 0);

   constant period : time := 10 ns;

BEGIN

    -- instantiate the Unit Under Test (UUT)
   uut: Xand generic map (width => 8)
        PORT MAP (
          clk => clk,
          A => A,
          B => B,
          C => C
        );

END;

Sadly I'm not sure how to write test, which i can later watch in gtkwave for my unit using generic parameter width. Well written test that will make for an example to another tests would be great.