VHDL testbench getting U in simulation waveform

I'm trying to implement a testbench using a Golden Model and a DUT, in this case I'm testing a full adder 4 bits. I'm always getting undefined at the signal s_dut while s_gm works just fine. I'm stuck on this for a while and I really don't know what the problem would be.

Here is the top module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity topmodule is
end topmodule;

architecture Behavioral of topmodule is

    component SomadorCompleto4bits_dut is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
             B : in  STD_LOGIC_VECTOR (3 downto 0);
             Cin : in  STD_LOGIC;
             S : out  STD_LOGIC_VECTOR (3 downto 0);
             Cout : out  STD_LOGIC);
    end component;

    component SomadorComOperador_golden_model is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
             B : in  STD_LOGIC_VECTOR (3 downto 0);
             S : out  STD_LOGIC_VECTOR (4 downto 0));
    end component;

    component testbench is
    port (s_dut, s_gm : in STD_LOGIC_VECTOR (4 downto 0);
            a, b : out STD_LOGIC_VECTOR (3 downto 0));
    end component;

    signal a, b : STD_LOGIC_VECTOR (3 downto 0);
    signal s_dut, s_gm : STD_LOGIC_VECTOR (4 downto 0); 


begin
    U0: SomadorCompleto4bits_dut port map(a, b, '0', s_dut (3 downto 0), s_dut(4));
    U1: SomadorComOperador_golden_model port map(a, b, s_gm);
    U2: testbench port map(s_dut, s_gm, a, b);
end Behavioral;

and here the testbench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity testbench is
    port (s_dut, s_gm : in STD_LOGIC_VECTOR (4 downto 0);
            a, b : out STD_LOGIC_VECTOR (3 downto 0));
end testbench;

architecture Behavioral of testbench is
begin
    process
        variable a_teste_in, b_teste_in : STD_LOGIC_VECTOR (3 downto 0);
    begin

        report "Iniciando teste..." severity NOTE;


        a_teste_in := "0000";
        b_teste_in := "0000";

        for i in 1 to 16 loop
            for j in 1 to 16 loop

                a <= a_teste_in;
                b <= b_teste_in;
                wait for 500 ns;

                assert (s_dut = s_gm) report "Falhou: i = " & integer'image(i) & " j = " & integer'image(j) severity ERROR;

                a_teste_in := a_teste_in + 1;

            end loop;

            b_teste_in := b_teste_in + 1;

        end loop;

        report "Teste finalizado!" severity NOTE;

        wait;

    end process;
end Behavioral;

I believe the error is somewhat related with the line:

U0: SomadorCompleto4bits_dut port map(a, b, '0', s_dut (3 downto 0), s_dut(4));

Thanks in advance!