Testbench in verilog produces errors saying LOC constraints are invalid

When I run my testbench, it produces the errors

ERROR:MapLib:30 - LOC constraint P126 on CLK is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P35 on SIGNAL is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P34 on x is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P33 on OUT.PAD is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

This is my first project in verilog, so I don't really know what's wrong. I'm trying to set up a simple testbunch like on page 8 of this for my code. The code with the UCF compiles just fine, so it must be something in the testbench. The testbench code is pretty similar to the code in the powerpoint, so I think it comes from my attempt to set local variables to certain values for the test and my not defining a different input. (I need to do this because to really test this it needs to have two inputs for SIGNAL, but I can't do this with the simple testbed described in the powerpoint. So I set the local variables to what they need to be and carry on.) However the errors seem to point to the UCF being the problem. So I don't really know what's going on.

Any help would be appreciated. I am using the Oracle VM Virtualbox ISE.

Code

module trapverilog(
    input CLK,
    input SIGNAL,
     input x,
     input SUM, // OUT is mapped to SUM on board
    output reg OUT
    );

reg[64:0] yregone;
reg[64:0] yregtwo;
reg[64:0] sum;

always @(posedge CLK)
begin
    yregtwo = yregone;
    yregone = SIGNAL;
    if (yregtwo != 0)
    begin
        sum = ((yregone + yregtwo)*x/2) + SUM; //treats x as plain h, change if treated as h/2
        OUT = sum;
    end
end

endmodule

User Config File

NET "CLK" LOC = P126;
NET "SIGNAL" LOC = P35 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; 
NET "x" LOC = P34 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "OUT" LOC = P33 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; 

Testbed

module testbed();
    reg CLK, SIGNAL, x, SUM;
    wire OUT;

// instantiate device under test
trapverilog dut(.CLK(CLK), .SIGNAL(SIGNAL), .x(x), .SUM(SUM), .OUT(OUT));

// apply inputs one at a time
initial begin
x = 1; CLK = 1; SUM = 0; trapverilog.yregone = 1; trapverilog.yregtwo = 2; #10; // apply input, wait
if (OUT !== 1.5) $display("failed."); // check
end
endmodule

endmodule