Isim is not testing all bits in test fixture

Hello I am trying to test all possible cases of inputs for my verilog code. I set it up with for loops.

for(sel = 0;sel < 4;sel=sel+1) begin
            for(a = 0;a < 8;a=a+1) begin
                    for(b = 0;b < 8;b=b+1) begin
                        #50;
                    end
            end
    end

It was working earlier but I must have changed something or Isim might have a bug. I initialized a,b, and sel too.

reg [2:0] a;
reg [2:0] b;
reg [1:0] sel;

But when I try to simulate the tb file, it only loops through b repeatedly! Why could this be? Ive been playing with it for a while and have had no luck.

Also when I change b bounds to <7, it will begin to loop through a, but i have to change a bounds to <7 to loop through sel. Although this partially works, it skips the cases of 111 for a and b and 11 for sel.