why do i need wait after assert in VHDL?

I've started learning VHDL, and on EdaPlayground there's always a wait; after assert(cond); in the testing file.

Could you please explain why do i need a wait; in the end? From my point of view, it should terminate right after execution, but it doesn't (and instead of terminating it lands into an infinite loop).

Here is the architecture i want to test :

use IEEE.std_logic_1164.all;

entity minority is
port(
  a: in std_logic;
  b: in std_logic;
  c: in std_logic;
  y: out std_logic
  );
end minority;

architecture impl of minority is
begin
   y <= '1' when (a and b and c) else '0';
end impl;

Here is the code for testing :

use IEEE.std_logic_1164.all;
 
entity testbench is
-- empty
end testbench; 

architecture tb of testbench is

-- DUT component
component minority is
port(
  a: in std_logic;
  b: in std_logic;
  c: in std_logic;
  y: out std_logic
  );
end component;

signal a1, b1, c1, y1: std_logic;

begin
  -- Connect DUT
  DUT: minority port map(a1, b1, c1, y1);

  process
  begin
    a1 <= '0';
    b1 <= '1';
    c1 <= '0';
    y1 <= '0';
    wait for 1 ns;
    assert(y1='0') report "Y is ok." severity error;
    wait; -- <-- without this line, the test starts to execute infinitely :(
  end process;
end tb;

Thank you for your answers!