How to design a test case to validate throttling capacity of a packet decoder?

I am implementing a packet decoder on a microcontroller. The packets are of 32-bytes each, received through a UART, every 10 milliseconds. The UART ISR(Interrupt Service Routine) keeps the received bytes in a ring buffer, and a thread scheduled every 7.5ms decodes the packets from ring buffer. There are instrumentation routines implemented to report the number of times ring buffer was full, error count after decoding, dropped bytes count. The microcontroller can send these packets back to PC running my test case through a different UART.

How do I design a test case to check if the system is meeting my performance requirements. These are the test cases which i should take care of --

1. The transmitter clock may run slightly faster( Sending a packet every 8ms, rather than the nominal 10ms).
2. The channel may introduce errors to data bits. There are checksum fields included in packet to cope up with that. How to simulate the channel errors?
3. The test case should be maintainable and extendable.

I already have a simulator through which i tested the decoder (implemented in microcontroller) for functional correctness. This simulator sends packets at a programmable intervals, and the value of data fields can be changed through a UI. How can this simulator be modified to do this?

Are there standard practices/test cases to do handle such throttling tests? Are there some edge cases iam missing? I need to make sure that the ring-buffer has enough space to handle the higher rates of packets send by the receiver.