Implementing a for loop in systemverilog

I want to generate an automated input stimulus for my DUT. This input is going to different modules at the same time and working on this data. I want my input to be generated in an increasing manner. Like 0000,0001,0010,0011...1111 I tried using a for loop but what it does is only uses the last data from the loop and works on that.

always_comb begin 

for (i=0, i<16; i=i+1) begin data <= i; end end