How can I connect two design units in modelsim simulation

I am trying to simulate two design units in modelsim without a common testbench. The two design units are a processor and an I/O device. I have written the processor and the I/O device is an IP core from Altera.

I need to verify that their interfaces match. I want to leave out a common testbench because it is much faster to write a small and simple testbench in tcl(do).

I start the simulation with:

vsim -i work.myProcessor work.AlteraIODevice

Can anyone tell me how I can connect two signal such that a signal from one entity drives the signal of the other entity?

Something like:

force /myProcessor/signalX /AlteraIODevice/signalY

I hope this makes sense.