Testbench Begginer Vhdl

Hello to everyone and thank you for your time. This is my testbench code for my rom.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;


entity rom_tb is 
end entity ;

architecture tb of rom_tb is 
component rom is 
port ( clk : in std_logic ;
       addr : in STD_LOGIC_VECTOR(2 downto 0);
       M : out STD_LOGIC_VECTOR(7 downto 0)
     ) ;
end component ;

signal clk_tb : std_logic := '0' ;
signal address_tb : integer := 0 ; 
signal data_out_tb : std_logic_vector( 7 downto 0 ) ;

begin 
uut : rom port map (
    clk => clk_tb ,
    addr => address_tb ,
    M => data_out_tb ) ;
------------------
clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        clk <= '1';
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;
   stim_proc: process
      begin         
           wait for 7 ns;
           address_tb <="001";
           wait for 3 ns;
           address_tb <="011";
           wait for 17 ns;
           address_tb <="111";
           wait;
     end process;

 end architecture ; 

Every time I try to simulate it I get this error:

[USF-XSim 62] 'compile' step failed with error(s) while executing 'C:/Users/George/rom/http://ift.tt/1LlcXuF' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.

My rom code is this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity rom is
    Port ( 
            clk : in std_logic ;
            addr : in STD_LOGIC_VECTOR(2 downto 0);
            M : out STD_LOGIC_VECTOR(7 downto 0)
            );
end rom;

architecture Behavioral of rom is
constant data0:STD_LOGIC_VECTOR(7 downto 0):="10000001";
constant data1:STD_LOGIC_VECTOR(7 downto 0):="10001001";
constant data2:STD_LOGIC_VECTOR(7 downto 0):="10110001";
constant data3:STD_LOGIC_VECTOR(7 downto 0):="10001101";
constant data4:STD_LOGIC_VECTOR(7 downto 0):="10000001";
constant data5:STD_LOGIC_VECTOR(7 downto 0):="10001001";
constant data6:STD_LOGIC_VECTOR(7 downto 0):="10111001";
constant data7:STD_LOGIC_VECTOR(7 downto 0):="11111001";


type rom_array is array (NATURAL range <>)of STD_LOGIC_VECTOR (7 downto 0);

constant rom: rom_array:=(
    data0, data1, data2, data3, data4, data5, data6, data7
    );

begin

process(clk)
variable j: integer;
begin
if( clk'event and clk = '1' ) then
j:=conv_integer(addr);
M <= rom(j);
end if;
end process;

end Behavioral;

If anyone knows what is going on please inform me. Thank you for your time again!