Long run test using VHDL

I'm trying to implement the long run test on a random generated 20kbit long bit stream to prove it's really random or not.

The long runs test: On the sample of 20,000 bits, the test is passed if there are no long runs. According to FIPS 140-2, A long run is defined to be a run of length 26 or more (of either zeros or ones).

I end up with this code below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LongRunTestModule is

    Port ( clk                      : in    STD_LOGIC;
           rst                      : in    STD_LOGIC;
              start                 : in    STD_LOGIC;
              noisein_longrun       : in    STD_LOGIC_VECTOR (15 downto 0);
              running_longrun       : out   STD_LOGIC;
              tok_longrun           : out   STD_LOGIC     
             );

end LongRunTestModule;

architecture Behavioral of LongRunTestModule is

shared variable twnty_k_bit_stream  :  bit_vector(19999 downto 0);
shared variable count:  integer := 0;
signal stream_received_succesfully  :   std_logic;

begin
    -- Process 1
    -- This pocess receives the 20kbit stream
    -- Then fires stream_received_succesfully as 1
    process (rst, clk, start)

    begin
        if rising_edge(clk) then
        if (start = '1') then

                count := count + 1;

                     if(count <= 16) then
                            twnty_k_bit_stream (twnty_k_bit_stream'LEFT downto noisein_longrun'LENGTH) :=
                            twnty_k_bit_stream (twnty_k_bit_stream'LEFT - noisein_longrun'LENGTH downto 0);
                            twnty_k_bit_stream (noisein_longrun'RANGE) := to_bitvector(noisein_longrun);
                    end if;
                    else
                        stream_received_succesfully <= '1';
                        count := 0;
            end if;
            end if;
    end process;


    process (clk, stream_received_succesfully)
    variable counter:  integer := 0;
    variable temp   :  bit_vector(19999 downto 0);
    begin
        if rising_edge(clk) then
            if (stream_received_succesfully = '1') then
                --while (twnty_k_bit_stream > 0) loop
                    temp := (twnty_k_bit_stream) and (twnty_k_bit_stream srl 1);
                    counter := counter + 1;
                --end loop;
            end if;
        end if;
    end process;
end Behavioral;

The algorithm simply does this. It receives a 16 bit signal for 1250 times to construct a 20kbit stream in first process. After 20 kbit is constructed, second process test if it has more than 26 consecutive ones. So I try to implement this approach using VHDL: Finding consecutive bit string of 1 or 0

Concept is AND a bit sequence with a shifted version of itself, you're effectively removing the trailing 1 from a row of consecutive 1's.

  11101111   (x)
& 11011110   (x << 1)
----------
  11001110   (x & (x << 1)) 
    ^    ^
    |    |

trailing 1 removed

To do this for n times I try to implement a while loop, but I can't write a condition statement as the twnty_k_bit_stream > 0. How can I implement this algorithm using VHDL?

My kind regards.